一、计数器仿真实验一 计数器一的手绘版RTL设计图 计数器一编译后生成的RTL图 程序代码
module top ( RST,CLK,CNT); input RST, CLK; output [3:0] CNT; reg [3:0] CNT; parameter CNT_MAX_VAL =5; always @ ( posedge RST or posedge CLK) begin if(RST) begin CNT <= 0; end else begin if(CNT < CNT_MAX_VAL) CNT <= CNT+ 1'b1; else CNT <= 0; end end endmodule仿真后的波形图 二、计数器实验仿真实验二 计数器二的手绘版RTL设计图 编译后生成的RTL设计图 程序编码
module top (CLK,RST,CNT); input CLK,RST; output [3:0] CNT; reg [3:0] CNT; integer CNT_MAX = 6; always @ ( posedge CLK or posedge RST) begin if(RST) begin CNT <= 0; CNT_MAX =6; end else if( CNT < CNT_MAX) begin CNT <= CNT + 1'b1; end else begin CNT <= 0; if(CNT_MAX < 9) CNT_MAX <= CNT_MAX + 1; else CNT_MAX = 6; end end endmodule仿真后的波形图
