开发环境如下
虚拟机:Oracle VM VirtualBox+ext拓展包
Linux:ubuntu14.04 LTS
VCS:2011.3
Verdi:2014.03
.bashrc新增环境变量如下:
export VERDI_HOME="/home/myhome/work/tool/Verdi" export DEBUSSY_HOME="/home/myhome/work/tool/Verdi" export LD_LIBRARY_PATH="/home/myhome/work/tool/Verdi/share/PLI/VCS/LINUX" export VCS_HOME="/usr/synopsys/E-2011.03" export PATH="$VCS_HOME/bin:$VERDI_HOME/bin:$VERDI_HOME/platform/LINUX/bin:$PATH" export LM_LICENSE_FILE="$VERDI_HOME/license/synopsys.dat" export VCS_ARCH_OVERRIDE=linux
在/home/myhome/sv/test0 文件夹下新建
flist.f
my_tb.v
counter.v
makefile
flist.f
+incdir+./ ./my_tb.v ./counter.v
my_tb.v
module my_tb(); reg clk; reg rstn; initial begin clk = 'd0; rstn = 'd0; #100 rstn = 'd1; end always #5 clk <= !clk; initial begin #1000 $finish(); end initial begin $fsdbDumpfile("tb.fsdb"); $fsdbDumpvars(0,"my_tb"); end wire [7:0] cnt; counter u_counter( .i_clk (clk ), .i_rstn (rstn ), .o_cnt (cnt ) ); endmodulecounter.v
module counter( input i_clk, input i_rstn, output reg [7:0] o_cnt ); always @(posedge i_clk or negedge i_rstn) begin if (!i_rstn) o_cnt <= 8'd0; else o_cnt <= o_cnt + 8'd1; end endmodule
makefile
#------------------------------------------------------------------------------------------------------- all : clean vcs verdi #------------------------------------------------------------------------------------------------------- vcs : vcs \ -f flist.f \ -fsdb -R +vc +v2k -sverilog -debug_all \ -P ${LD_LIBRARY_PATH}/novas.tab ${LD_LIBRARY_PATH}/pli.a \ | tee vcs.log #------------------------------------------------------------------------------------------------------- verdi : verdi \ -sverilog +v2k -f flist.f -ssf tb.fsdb -nologo #------------------------------------------------------------------------------------------------------- clean : rm -rf *~ core csrc simv* vc_hdrs.h ucli.key urg* *.log novas.* *.fsdb* verdiLog 64* DVEfiles *.vpd #-------------------------------------------------------------------------------------------------------