module decode
(
input clk,
input rst,
output [8:0]seg_led1, //显示位数
output [8:0]seg_led2
);
reg [8:0]seg[9:0]; //9位位宽的寄存器数组
parameter div=6000000;
reg [23:0]cnt;
reg clk_div;
reg [3:0]ge;
reg [3:0]shi;
initial
begin
seg[0] = 9'h3f;
seg[1] = 9'h06;
seg[2] = 9'h5b;
seg[3] = 9'h4f;
seg[4] = 9'h66;
seg[5] = 9'h6d;
seg[6] = 9'h7d;
seg[7] = 9'h07;
seg[8] = 9'h7f;
seg[9] = 9'h6f;
end
always @(posedge clk or negedge rst) //分频 1hz
begin
if(!rst)begin
clk_div<=0;
cnt<=0;
end
else if(cnt<(div-1))begin
cnt<=cnt+1;
//clk_div<=0;
end
else begin
cnt<=0;
clk_div<=~clk_div;
end
end
always @(posedge clk_div or negedge rst)begin
if(!rst)begin
ge<=0;
shi<=0;
end
else if((shi*10+ge)==99)begin
shi<=0;
ge<=0;
end
else if(ge==9)begin
ge<=0;
shi<=shi+1;
end
else ge<=ge+1;
end
assign seg_led1=seg[ge];
assign seg_led2=seg[shi];
endmodule
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