xiaoxiao2021-02-28  7

1 USB 3.0 PIPE PHY 1.1 SS PHY电流源 CML电流源串联在NMOS管的Source中,电流是16 mA,所以差分电压摆幅是16 mA x (50 // 50) x 2 = 800 mV。 1.2 PIPE PHY数据线宽度 USB 3.0 PIPE PHY(SerDes)的数据线宽度是可以设置的,最大宽度分别是TX 32bit、RX 32bit,需要根据PIPE PHY的接口频率来设置数据线宽度。如果PIPE PHY运行在128MHz,那么TX和RX的数据线宽度都是32bit;如果PIPE PHY运行在256MHz,那么TX和RX的数据线宽度都是16bit。 USB 3.0 Gen1的速度5Gbps,是指TX和RX的速率都是5Gbps(128MHz * 4bytes或者256MHz * 2bytes)。 USB 3.0 Gen1的速度5Gbps(625MB/s),协议开销(overhead)占用了20%带宽,所以实际有效速度是500MB/s。 USB 3.0 TX或者RX的传输速率虽然是5Gbps,但实际上数字信号的方波频率是2.5GHz(传输2个bit对应一个方波)。 Intel平台xHCI的物理层名字是ModPHY(High Speed I/O Modular Physical Layer for Intel USB 3.0)。 1.3 Lane polarity reversal USB SS SerDes支持差分信号极性反转 You can swap the SSTX and SSRX pairs but not the USB2 (D+/D-) pair. This is because, during SuperSpeed enumeration, certain training sequences (called TSEQs) are sent and the D10.2 symbol in this is used to detect if lane polarity inversion is done (refer to section 6.4.2 of the USB 3.0 spec). However, such lane inversion detection is not done in USB 2.0 enumeration. This inversion is recommended if your design will cause SSTX+ and SSTX- (or the RX pairs) to cross each other. Then you can swap these pins to avoid this crossing. Polarity detection is done automatically by the USB 3.0 PHY during link training, as defined in the USB 3.0 specification, section 6.4.2. Doing so does not require changes to the device firmware. Given the different USB connector pin-outs, you can use the polarity inversion mechanism to ensure that USB traces do not cross each other. 1.4 Receiver Detection Link层LTSSM会周期性驱动PHY的PIN TxDetectRx到高,让PHY做Receiver Detection。Receiver的SSRX+/-上各有一个等效的50欧姆下拉电阻,并联形成25欧姆电阻。 设备连接前的充放电时间常数T = R_Detect * C_Parasitic 设备连接后的充放电时间常数T = (R_Detect + R_Term) * (C_AC + C_Parasitic) 2 Link Layer 2.1 LTSSM Figure 2-1 LTSSM Diagram


SS.Disabled - 产生中断 SS.Inactive - 产生中断 Compliance Mode - 不产生中断 khubd:基于外部USB HUB设计 2.2 TX - Compliance mode CP0 is sent by DUT TX+/- firstly, when trigger device sends Ping.LFPS to DUT RX+, then DUT will toggle CP1/CP7/CP8 to oscilloscope via TX+/-. CP1: SSC,调制三角波(30~33kHz) Enter compliance mode : 1)  Plug in USB host cable w/o fixture connected 2)  Disable any power management features: a.  echo on > /sys/bus/usb/usb1/power/control b.  echo on > /sys/bus/usb/usb2/power/control 3)  /system/bin/r 0xA800430 0x10340 4)  Plug in the USB test fixture 5)  Compliance pattern is generated on the scope 2.3 RX - Loopback mode 这里的环回表示Link层,不是PHY层的PCS或者PMA环回。 Figure 2-2 USB RX Test-Loopback

Need a BERT(Bit Error Rate Tester, 误码率测试仪) Polling.LFPS->65536 Rx.EQ->256 TS1->256 TS2(TS2 Symbol 5 bit2, Loopback)->Loopback Verilog big endian data, 0xBC means COMMA Rx.EQ: 32'hBCFF17C0, 32'h14B2E702, 32'h82726E28, 32'hA6BE6DBF, 32'h4A4A4A4A, 32'h4A4A4A4A, 32'h4A4A4A4A, 32'h4A4A4A4A TS1: 32'hBCBCBCBC, 32'h00004A4A, 32'h4A4A4A4A, 32'h4A4A4A4A TS2: 32'hBCBCBCBC, 8'h00, {4'h0, 1'h0, loopback > 0, 1'h0, hot_reset_count > 0}, 16'h4545, 32'h45454545, 32'h45454545 2.4 Stream ID - 同一个端点的MUX机制 - 使用ERDY(Stream ID, NumP)通知host,命令是depcmd struct usb_request {     [...]     unsigned        stream_id:16;     [...] }; 3 libusb库的使用 Read my blog “Android libusb库的使用”。 4 URLs daisho USB LatticeECP (EConomy Plus) enjoy-digital/usb3_pipe [RFC v2 00/22] USB 3.0 hub support & xHCI split roothub for 2.6.38 5 Abbreviations ARC:Argonant RISC Core AT91SAM9260:SAM means Smart ARM-based Microcontroller ATMEL SAMBA:ATMEL Smart ARM-based Microcontroller Boot Assistant CC2530:TI ChipCon2530 DWC2:Design Ware Controller 2,Apple的嵌入式设备,包括iPad和iPhone都是使用的DWC2 EOM: On chip Eye Opening Monitor for USB PIPE PHY receiver side HUB3CV:USB 3 Hub Command Verifier Ver. ISP1161:Philips' Integrated host Solution Pairs 1161,“Firms introduce USB host controllers”, LatticeECP: EConomy Plus, integrate USB SerDes PAM-4:每个符号表示2个bit,眼图有3个眼睛;而NRZ眼图只有一个眼睛 Quirks:the attributes of a device that are considered to be noncompliant with expected operation SL811HS:Cypress/ScanLogic 811 Host/Slave,性能上与ISP1161(Integrated host Solution Pairs 1161)相当 TDI:TransDimension Inc.,该公司首先发明了将TT集成到EHCI RootHub中的方法,这样对于嵌入式系统来说,就省去了OHCI/UHCI的硬件,同时降低了成本,作为对该公司的纪念,Linux内核定义了宏ehci_is_TDI(ehci);产品UHC124表示USB Host Controller;收购了ARC USB技术;现已被chipidea收购,chipidea又被mips收购 TLV:TI Low Value,高性价比 TPS:TI Performance Solution TT:Transaction Translator(事务转换器,将USB2.0的包转换成USB1.1的包) U0:USB SS link is Up USB BH reset:Bigger Hammer or Brad Hosler,表示warm reset;you may be confused why the USB 3.0 spec calls the same type of reset "warm reset" in some places and "BH reset" in other places. "BH" reset is supposed to stand for "Big Hammer" reset, but it also stands for "Brad Hosler". Brad died shortly after the USB 3.0 bus specification was started, and they decided to name the reset after him. The suggestion was made shortly before the spec was finalized, so the wording is a bit inconsistent. usb3_mifgen:Altera Memory Initialization File VNA:Vector Network Analyzer,矢量网络分析仪